Multiport memory cell having improved density area

ABSTRACT

A multiport memory cell having improved density area is disclosed. The memory cell includes a data storing component, a first memory access component coupled to a first side of the data storing component, a second memory access component coupled to a second side of the data storing component, first and second bit lines coupled to the first memory access component, first and second bit lines coupled to the second memory access component, first and second write lines coupled to the first memory access component and first and second write lines coupled to the second memory access component. The multiport memory cell also includes a read/write assist transistor, coupled to load transistors of the data storing component, that during read operations is activated for the duration of the read operation and during write operations is activated to impress the desired voltage level before or after one or more memory access components activated as a part of the write operation are deactivated.

RELATED APPLICATIONS

This application is a continuation of and claims priority to the copending application U.S. Non-provisional patent application Ser. No. 14/216,855, filed on Mar. 17, 2014, entitled “Multiport Memory Cell Having Improved Density Area,” which claims priority to US Provisional Patent Application Ser. No. 61/800,885, filed on Mar. 15, 2013, entitled “Multiport Memory Cell Having Improved Density Area,” which are hereby incorporated herein by reference in their entirety.

BACKGROUND

FIG. 1 shows a multiport cell SRAM 150 that has true/complement pairs of wires that form bit line pairs or ports. The multiport cell SRAM 150 includes MNTT (true side pass component), MPLT (true load transistor), MPLC (complement side load transistor), MNDT (true side drive transistor), MNDC (complement side drive transistor), MNTC (complement side pass component), W0 (word line topside), W1 (word line bottom), B0t (true side bit line 1), B1T (true side bit line 2), B0C (complement side bit line 1) and B1C (complement side bit line 2). Referring to FIG. 1, transistors MPLT, MPLC, MNDT and MNDC constitute the data holding portion of SRAM memory cell 150. Transistors MNTT and MNTC are pass gates.

Read stability and writeability are parameters that are used to assess the operation of memory cells. SRAM cells are considered stable if they can be read without the read operation causing the state of the data that is stored within them to change. As regards reads, during a read operation, turning on the pass gates, which are controlled by the word lines, results in a beta ratio effect on the low side of the memory cell between MNTT and MNDT. The increasing voltage on node MT turns on MNDC and causes a lowering of the voltage on node MC. A size ratio must be utilized as a part of the design implementation that prevents a feedback to node MT which would be positively reinforcing (causing read instability). Typical ratios of WMNDT/WMNTT=WMNDC/WMNTC of approximately 2 are considered good design practice.

As regards writes, during write operations one of the pair of bit lines is transitioned low (Vss). An internal change of state results from the low bit line pulling the high node toward Vss (current Ids flows through transfer gate MNTC) and is assisted by the MNTT gate pulling MT up toward Vdd. The MNTC MOSFET gate must have sufficient current to pull the high node lower (MPLC is acting like a resistor in the linear region of MOSFET operations). The voltage drop across the MPLC must be high enough to induce unstable feedback to change state. Process statistical variability can result in weak N/strong P conditions which can result in the inability to write. Ratioed memory cells can exhibit difficulty at lowered Vdd supply.

FIG. 2 shows another conventional multiport SRAM memory cell 250. SRAM memory cell 250 includes data storage and pass components similar to those shown in FIG. 1. In addition to components shown in FIG. 1, SRAM memory cell 250 includes separate read transistors that are coupled to separate read word lines Rwl0 and Rwl1 (these word line a separate from write word lines Wwl0 and Wwl1). Transistors MNTT and MNTC are pass gates. SRAM memory cell 250 features separate read and write ports (as part of a so called 8T cell) that improves writeability and provides low Vdd functionality. As regards readability, read operations do not activate transistors that are connected to internal nodes, i.e. only gate connections resulting in minimal read disturbance of internal storage nodes. Typically, for “single ended” reads, true/complement bit lines are not relevant for stability. As regards writeability, writes are improved since transistors can be beta ratioed to favor writes since activation of a write word line implies a state change is intended (contrast to shared port cell).

FIG. 1 shows a multiport cell SRAM 150 that has true/complement pairs of wires that form bit line pairs or ports. The multiport cell SRAM 150 includes MNTT (true side pass component), MPLT (true load transistor), MPLC (complement side load transistor), MNDT (true side drive transistor), MNDC (complement side drive transistor), MNTC (complement side pass component), W0 (word line topside), W1 (word line bottom), B0t (true side bit line 1), B1T (true side bit line 2), B0c (complement side bit line 1) and B1C (complement side bit line 2). Referring to FIG. 1, transistors MPLT, MPLC, MNDT and MNDC constitute the data holding portion of SRAM memory cell 150. Transistors MNTT and MNTC are pass gates.

Disadvantages of SRAM memory cell 250 is that multiple separate write/read wordline wires are required and separate write/read bit lines (ports) are used. Area usage is high due to large number of wire pitches. Active transistors are also high due to separate active area for read and write transistors.

Increasing the memory cell density of memory cell arrays increases the data storage capacity of memory cell arrays. Many conventional designs feature port intensive memory cell structures. Such structures are implemented using increased numbers of wires/lines (e.g., bit lines and word lines) that increase power consumption and require more area. In addition, some conventional designs utilize more transistors that also require more area.

SUMMARY

Many conventional designs feature port intensive memory cell structures. Such structures are implemented using increased numbers of lines (e.g., bit lines and word lines) that increase power consumption and require more area. In addition, some conventional designs utilize more transistors that also require more area. A multiport memory cell having improved density area is disclosed that addresses the aforementioned shortcomings of conventional processor designs. However, the claimed embodiments are not limited to implementations that address any or all of the aforementioned shortcomings. The multiport memory cell having improved density area includes a data storing component, a first memory access component coupled to a first side of the data storing component, a second memory access component coupled to a second side of the data storing component, first and second bit lines coupled to the first memory access component, first and second bit lines coupled to the second memory access component, first and second write lines coupled to the first memory access component and first and second write lines coupled to the second memory access component. The multiport memory cell also includes a read/write assist transistor, coupled to load transistors of the data storing component, that during read operations is activated for the duration of the read operation and during write operations is initially deactivated assist with the write operation. Subsequently, during the write operation the read/write assist transistor is activated to impress the desired voltage level before or after one or more memory access components activated as a part of the write operation are deactivated.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention, together with further advantages thereof, may best be understood by reference to the following description taken in conjunction with the accompanying drawings in which:

FIG. 1 shows a multiport cell SRAM that has true/complement pairs of wires that form bit line pairs or ports.

FIG. 2 shows another conventional multiport SRAM memory cell.

FIG. 3 shows an exemplary operating environment of an SRAM memory cell according to one embodiment.

FIG. 4A shows SRAM memory cell that is configured for density/area maximization/minimization according to one embodiment.

FIG. 4B illustrates a read operation of and SRAM memory cell that is configured for density/area maximization/minimization according to one embodiment.

FIG. 4C illustrates a write operation of and SRAM memory cell that is configured for density/area maximization/minimization according to one embodiment.

FIG. 5A shows a flowchart of the steps performed in a method for reading an SRAM memory cell according to one embodiment.

FIG. 5B shows a flowchart of the steps performed in methods for writing to an SRAM memory cell according to one embodiment.

It should be noted that like reference numbers refer to like elements in the figures.

DETAILED DESCRIPTION

Although the present invention has been described in connection with one embodiment, the invention is not intended to be limited to the specific forms set forth herein. On the contrary, it is intended to cover such alternatives, modifications, and equivalents as can be reasonably included within the scope of the invention as defined by the appended claims.

In the following detailed description, numerous specific details such as specific method orders, structures, elements, and connections have been set forth. It is to be understood however that these and other specific details need not be utilized to practice embodiments of the present invention. In other circumstances, well-known structures, elements, or connections have been omitted, or have not been described in particular detail in order to avoid unnecessarily obscuring this description.

References within the specification to “one embodiment” or “an embodiment” are intended to indicate that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. The appearance of the phrase “in one embodiment” in various places within the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. Moreover, various features are described which may be exhibited by some embodiments and not by others. Similarly, various requirements are described which may be requirements for some embodiments but not other embodiments.

Some portions of the detailed descriptions, which follow, are presented in terms of procedures, steps, logic blocks, processing, and other symbolic representations of operations on data bits within a computer memory. These descriptions and representations are the means used by those skilled in the data processing arts to most effectively convey the substance of their work to others skilled in the art. A procedure, computer executed step, logic block, process, etc., is here, and generally, conceived to be a self-consistent sequence of steps or instructions leading to a desired result. The steps are those requiring physical manipulations of physical quantities. Usually, though not necessarily, these quantities take the form of electrical or magnetic signals of a computer readable storage medium and are capable of being stored, transferred, combined, compared, and otherwise manipulated in a computer system. It has proven convenient at times, principally for reasons of common usage, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, or the like.

It should be borne in mind, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. Unless specifically stated otherwise as apparent from the following discussions, it is appreciated that throughout the present invention, discussions utilizing terms such as “receiving” or “biasing” or “determining” or “placing” or the like, refer to the action and processes of a computer system, or similar electronic computing device that manipulates and transforms data represented as physical (electronic) quantities within the computer system's registers and memories and other computer readable media into other data similarly represented as physical quantities within the computer system memories or registers or other such information storage, transmission or display devices.

Exemplary Operation Environment of an SRAM Memory Cell Configured for Density/Area Maximization According to One Embodiment

FIG. 3 shows an exemplary operating environment 300 of SRAM memory cell(s) 350 according to one embodiment. SRAM memory cell 350 includes a shared word line multiport cell structure that enables less area usage than some conventional cells that use separate read/write ports and involves a large number of word line pitches. SRAM memory cell 350 features a sizing of transistors and the use of a MOSFET that facilitates read stability and writeability in a memory cell structure that enables less area usage than some conventional memory cells. FIG. 3 shows CPU 301, L1 cache 303, L2 cache 305, SRAM memory cells 350 and main memory 311.

Referring to FIG. 3, CPU executes instructions and carries out accesses of L1 cache 303, L2 cache 305 and main memory 311 that involve storing and loading data and instructions. In one embodiment, L1 cache 303 and L2 cache 305 comprise SRAM memory cells 350. SRAM memory cells 350 are described herein below in detail in conjunction with FIG. 3. In one embodiment, main memory 311 constitutes larger memory than L1 cache 303 and L2 cache 305 and can comprise DRAM memory cells. In other embodiments main memory 311 can comprise other types of memory cells.

SRAM Memory Cell

FIG. 4A shows an SRAM memory cell 350 that is configured for density/area maximization according to one embodiment. FIG. 4A shows MNTT 351 (true side pass component), MPLT 353 (true side load transistor), MPLC 355 (complement side load transistor), MNDT 357 (true side drive transistor), MNDC 359 (complement side drive transistor), MNTC 361 (complement side pass transistor), W0C 363 (topside word line complement), W0T 365 (topside word line true), W1T 367 (bottom word line true), W1C 369 (bottom word line complement), B0T 371 (first true side bit line), B1T 373 (second true side bit line), B0c 375 (first complement side bit line) and B1C 377 (second complement side bit line) and MPW 379 (write margin assist/read stability assist transistor). Referring to FIG. 4A, transistors MPLT 353, MPLC 355, MNDT 357 and MNDC 359 constitute the data holding portion of SRAM memory cell 350. Transistors MNTT 351 and MNTC 361 are pass gates.

In one embodiment, as regards read operations, MPLT 353 and MPLC 355 are sized (increased with respect to prior art counterparts) to prevent a change of the cell state until transistor MPW 379 is deactivated. In addition, MPLT 353 and MPLC 355 are sized to allow activation of a single transfer gate WC or WT to allow single ended reads without cell instability. During write operations true/complement (differential write function) is allowed by activating both the W0C and W0T or W1C and W1T. Deactivating MPW 379 allows nodes MC, MT to become easier to transition by reducing the ability of MPLT 353, MPLC 355 to stop a write transition. Node PW can also be driven low to make more certain that MPLT 353, MPLC 355 present increasing impedances (not shown). The source node of MPLT 353 and MPLC 355 will move from Vdd toward Vss by virtue of a write current through MNTC 361 turning off MPLC 355 a delay time later. In one or more embodiments, MPW 379 can be external to memory cell 350 as is shown in FIG. 4A. In one or more other embodiments, MPW 379 can be internal to memory cell 350 to reduce capacitive effects. In one or more embodiments, memory cell(s) 350 can be used as a part of cache memory systems as shown in FIG. 4A. Moreover, in one or more embodiments, memory cell(s) 350 can be used to form CPU registers and/or register files of CPU execution units, whether or not memory cells 350 are used as a part of cache memory systems.

Opeation

FIGS. 4B and 4C illustrate read and write operations performed as a part of the operation of SRAM memory cell 350 that is configured for density/area maximization according to one embodiment. These operations, which relate to read and write operations, are illustrated for purposes of clarity and brevity. It should be appreciated that other operations not illustrated by FIGS. 4B and 4C can be performed in accordance with one embodiment.

Read Operation

Referring to FIG. 4B, at A, bit lines B1T 373, B0T 371, B1C 377 and B0C 375 are biased to a high level (for example the level of the supply voltage).

At B, a low level is placed onto the gate terminal of MPW 379. MPW 379 is turned on and is kept on for the duration of the read operation.

For a single ended read involving, for example, wordline W0T 365, W0T is driven high such that a high voltage is placed onto the gate terminal of pass gate MNTT 351. If pass gate MNTT 351 turns on, it provides an indication that node MT is low and that a low state is stored in memory cell 350. If the pass gate does not conduct, it provides an indication that node MT is high and that a high state is stored in the memory cell.

At C, the indication is provided to a peripheral circuit.

Write Operation

Referring to FIG. 4C, at A, MPW 379 is turned off. In one embodiment, MPW 379 can be turned off either before or after pass gate MNTT 351 is turned on (such that in the case where a low voltage level is being written into memory cell 350 read/write assist transistor MPW 379/MPLT 353 does not fight the impressing of the low voltage level therein).

At B, bit lines B1T 373, B0T 371, B1C 377 and B0C 375 are biased (to a low voltage level if the level to be written is low and to a high voltage level if the level to be written is high).

At C, for example, when a high voltage is to be written to the memory cell, a high voltage is placed onto the gate terminal of pass gate MNTT 351. For a single ended writes involving wordline W0T 365, W0T 365 is driven high such that the high voltage is placed onto the gate terminal of pass gate MNTT 351. If pass gate MNTT 351 turns on, it provides an indication that node MT is high and that a high state is stored in the memory cell no change of node state occurs. If pass gate MNTT 351 turns on, due to memory node MT in low state and bitline B0T in low state, no change of memory node MT occurs (both nodes at same voltage state). If bitline MT is initially high the conduction of MNTT 351 will drive node MT low. If pass gate MNTT 351 does not conduct bitline B0T is low, it provides an indication that node MT is low and that a low state is stored in the memory cell node MT (that a low state does not have to be changed). Because pass gate MNTT 351 does not conduct the stored state will not be changed. If pass gate MNTT 351 conducts and memory bitline node B0T is high, it indicates that node MT is low requiring transition to the high MT state. A beta ratioed condition will prevent write until node PW is lowered in voltage and MPLC 355 drives node MC to a lowered voltage condition to reduce the drive of MNDT 357 resulting in MNTT 351 driving node MT to vt threshold below positive supply and this state is further reinforced by MNDC driving node MT to negative supply.

At D, MPW 379 is turned on to ensure that the level that is written into the cell is maintained. Any intermediate voltage resulting from the write operation and pass transistor vt down states will be reinforced at this point in the operation.

Method for Operating an SRAM Memory Cell Configured for Density/Area Maximation/Minimization According to One Embodiment According to One Embodiment

FIGS. 5A and 5B show flowcharts 500A and 500B of the steps performed in methods for reading and writing to an SRAM memory cell according to one embodiment. The flowchart includes processes that, in one embodiment can be carried out by processors and electrical components under the control of computer-readable and computer-executable instructions. Although specific steps are disclosed in the flowcharts, such steps are exemplary. That is the present embodiment is well suited to performing various other steps or variations of the steps recited in the flowchart. Although specific steps are disclosed in the flowcharts, such steps are exemplary. That is the present embodiments are well suited to performing various other steps or variations of the steps recited in the flowcharts.

Read Operation

Referring to FIG. 5A, at 501A, bit lines are biased to a high voltage level.

At 503A, read/write assist transistor is turned on and is kept on for the duration of the read of the read operation.

For a single ended read involving wordline W0T (e.g., 365 in FIG. 4A), W0T (e.g., 365 in FIG. 4A) is driven high such that a high voltage is placed onto the gate terminal of pass gate MNTT (e.g., 351 in FIG. 4A). If pass gate MNTT (e.g., 351 in FIG. 4A) turns on, it provides an indication that node MT is low and that a low state is stored in the memory cell. If the pass gate does not conduct, it provides an indication that node MT is high and that a high state is stored in the memory cell.

At 505A, the indication is sensed and provided to a peripheral circuit. It should be appreciated that reads involving other wordlines operate similarly.

Write Operation

Referring to FIG. 5B, at 501 B, read/write assist transistor is turned off.

At 503B, bit lines are biased to a voltage level that is intended to be written into the memory cell. Alternately, the bitlines could be changed to the write state following wordline transition.

At 505B, for single ended writes the involved wordline is driven high such that a high voltage is placed onto the gate terminal of the pass gate that is involved in the write. If the pass gate turns on, it provides an indication that node MT is high and that a high state is stored in the memory cell. The conduction of the pass gate will cause the voltage that is stored in the memory cell to change. If the pass gate does not conduct, it provides an indication that state does not have to be changed. Moreover, because the pass gate is not caused to conduct the stored state will not be changed.

At 507B, the read/write assist transistor is turned on to ensure that the level that is written into the cell is driven to the high voltage level. In one or more embodiments, the wordline can be turned off following the turn on of the read/write assist transistor. In one or more other embodiments, the wordline can be turned off before the turn on of the read/write assist transistor. In one or more other embodiments, after 507B, if the memory node voltage state is different from the bitline voltage level, a memory cell node will change voltage states. This voltage level will be intermediate since the pass gate is not capable of driving to the high voltage state or node PW is at an intermediate state. In this case, read/write assist transistor can be turned on to drive the memory cell node from the intermediate state to the rail state.

A multiport memory cell having improved density area is disclosed. The memory cell includes a data storing component, a first memory access component coupled to a first side of the data storing component, a second memory access component coupled to a second side of the data storing component, first and second bit lines coupled to the first memory access component, first and second bit lines coupled to the second memory access component, first and second write lines coupled to the first memory access component and first and second write lines coupled to the second memory access component. The multiport memory cell also includes a read/write assist transistor, coupled to load transistors of the data storing component, that during read operations is activated for the duration of the read operation and during write operations to impress the desired voltage level is activated before or after one or more memory access components activated as a part of the write operation are deactivated. Although embodiments described herein and depicted in the accompanying Figures are discussed and shown as incorporating specific parts (transistor types etc.), the invention is not limited to such implementations, for example embodiments that utilize parts or part types other than those described herein but that provide the same functionality that is described herein can be implemented in accordance with the invention.

Although many of the components and processes are described above in the singular for convenience, it will be appreciated by one of skill in the art that multiple components and repeated processes can also be used to practice the techniques of the present invention. Further, while the invention has been particularly shown and described with reference to specific embodiments thereof, it will be understood by those skilled in the art that changes in the form and details of the disclosed embodiments may be made without departing from the spirit or scope of the invention. For example, embodiments of the present invention may be employed with a variety of components and should not be restricted to the ones mentioned above. It is therefore intended that the invention be interpreted to include all variations and equivalents that fall within the true spirit and scope of the present invention. 

We claim:
 1. A memory cell, comprising: a data storing component comprising a plurality of load transistors; a first memory access component coupled to the data storing component; a second memory access component coupled to the data storing component; a plurality of lines coupled to the first memory access component and the second memory access component; and a read/write assist transistor coupled to the plurality of load transistors of the data storing component, wherein the plurality of load transistors is configured to prevent a change in a state of the data storing component until the read/write assist transistor is deactivated.
 2. The memory cell of claim 1, wherein the plurality of load transistors is configured to allow activation of a transfer gate to allow single ended read operations.
 3. The memory cell of claim 1, wherein the read/write assist transistor is configured to be activated for the duration of a read operation and during write operations, the read/write assist transistor is configured to be activated to impress a desired voltage level before or after deactivation of one or more memory access components that are activated as a part of the write operation.
 4. The memory cell of claim 1, wherein the plurality of lines comprise: first and second bit lines coupled to the first memory access component; first and second bit lines coupled to the second memory access component; first and second write lines coupled to the first memory access component; and first and second write lines coupled to the second memory access component.
 5. The memory cell of claim 4, wherein the memory cell is configured for a differential write, wherein either the first and second write lines coupled to the first memory access component or the first and second write lines coupled to the second memory access component are activated.
 6. The memory cell of claim 4, wherein the memory cell is configured for a single ended write operation, wherein a single write line and a single transistor of one of the first memory access component and the second memory access component is activated.
 7. The memory cell of claim 1, wherein the read/write assist transistor is coupled to terminals of the plurality of load transistors of the memory cell.
 8. The memory cell of claim 1, wherein the read/write assist transistor is located inside the memory cell.
 9. The memory cell of claim 1, wherein the memory access components are coupled to respective internal nodes of the memory cell.
 10. The memory cell of claim 1, wherein the memory cell comprises nodes that are coupled to true and complement voltage levels.
 11. A processor, comprising: a CPU; a memory component coupled to the CPU, wherein the memory component comprises a memory cell comprising: a data storing component comprising a plurality of load transistors; a first memory access component coupled to a first side of the data storing component; a second memory access component coupled to a second side of the data storing component; a plurality of lines coupled to the first memory access component and the second memory access component; and a read/write assist transistor coupled to the plurality of load transistors of the data storing component, wherein the plurality of load transistors is sized to prevent a change in a state of the data storing component until the read/write assist transistor is deactivated.
 12. The memory cell of claim 11, wherein the plurality of load transistors is sized to allow activation of a transfer gate to allow single ended read operations.
 13. The memory cell of claim 11, wherein the memory component is selected from the group consisting of a register and a cache memory.
 14. The memory cell of claim 11, wherein the read/write assist transistor is configured to be activated for the duration of a read operation and during write operations the read/write assist transistor is configured to be activated to impress a desired voltage level before or after deactivation of one or more memory access components that are activated as a part of the write operation.
 15. The processor of claim 11, wherein the plurality of lines of the memory cell comprises: first and second bit lines coupled to the first memory access component; first and second bit lines coupled to the second memory access component; first and second write lines coupled to the first memory access component; and first and second write lines coupled to the second memory access component.
 16. The processor of claim 15, wherein the memory cell is configured for a differential write, wherein either the first and second write lines coupled to the first memory access component of the first and second write lines coupled to the second memory access component are activated.
 17. The processor of claim 15, wherein the memory cell is configured for a single ended write operation, wherein a single write line and a single transistor of one of the first memory access component and the second memory access component is activated.
 18. A method for accessing a memory cell, comprising: in a mode comprising write operation: biasing one or more bit lines to either a high or low voltage state; placing a high voltage level onto the gate of a memory access component; turning a read/write assist transistor on to impress the desired voltage level after the memory access component is turned off.
 19. The method of claim 18 comprising executing a differential write wherein either first and second write lines coupled to a first memory access component or first and second write lines coupled to a second memory access component are activated.
 20. The method of claim 18 comprising executing a single ended write operation wherein a single write line and a single transistor of one of a first memory access component and a second memory access component is activated. 